Design Verification Engineer (3 Years),Appex Semiconductors

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  • Design Verification Engineer (3 Years) Description AppEx is looking for a smart and enterprising engineers with expert knowledge in IP and Sub system verification. This role will include 1. Create Verification Plans For Sub systems and IP Blocks 2. Create Testbenches In SystemVerilog With UVM methodology 3. Utilize Advanced Verification Techniques Experience 3-5 Years Experience In Design Verification Engineer Primary Skills 1. Experience With SystemVerilog 2. Experience With The UVM Reuse Methodology 3. Experience With Advanced Verification Techniques Like Constrained Random Generation, Functional Coverage, Assertions And Formal Verifiers 4. Good Problem Solving And Debugging Skills Secondary Skills 1. Experience With One Or more simulators from the major EDA suppliers (Cadence, Mentor Or Synopsys) 2. Good Software Skills In Object Oriented Programming (OOP), C, C , Perl, Tcl, Csh Job Location Bangalore, Noida, Chennai, Hyderabad, Coimbatore