Senior Hardware Verification Engineer

The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC). You will architect advanced UVM-based testbenches, define exhaustive verification plans, and lead the “coverage closure” process to ensure the design meets all architectural specifications before tape-out. Key Responsibilities Verification Strategy: Define and document the verification plan (vPlan), including test scenarios, checkers, and f…